This invention relates to an architecture for integrated circuits having intellectual property (IP) blocks, and more particularly, to circuitry that supports the embedding of large IP blocks into programmable circuitry.
Programmable integrated circuits are a type of integrated circuit that can be programmed by a user to implement a desired custom logic function. In a typical scenario, a logic designer uses computer-aided design tools to design a custom logic circuit that performs custom logic functions. As the complexity of design that computer-aided design tools are capable of realizing increases, the number of interconnections between circuit elements on an integrated circuit rapidly increases in magnitude.
Intellectual property (IP) blocks correspond to circuitry with a lesser degree of programmability and configurability than logic fabric in programmable circuitry. The integration of large IP blocks that are used or utilized by user logic regions in the programmable circuitry often causes degraded timing closure, which limits the performance of programmable circuitry.
User logic regions require interconnections between themselves (i.e., between individual logic sectors in the user logic regions) and also require interconnections to the IP blocks that are formed adjacent to the user logic regions. Often, only a limited region around IP blocks is available for routing interconnections between the logic regions to the IP blocks. These limitations, on the area in which interconnects can be routed, often cause interconnect routing congestion which limits the maximum achievable performance of programmable circuitry. Conventional architectures for designing programmable circuitry place IP blocks in a manner that results in interconnect congestion or blockages where a high volume of interconnections are routed through a limited area in order to communicate with IP blocks. Moreover, interconnections such as vertical interconnections (or, V-wires) have a finite, or limited, availability in a given area, which may be exhausted due to routing congestion that results from traditional architectures, further limiting the achievable functionality in a programmable circuit design that interfaces with IP blocks.
Therefore, improved architectures for integrating IP blocks into programmable circuitry are required.